Close Topic Options

Hi,

I guess this isn't exactly winasm related, but could someone explain the idiv instruction. I read that IDIV divides EDX:EAX by the operand in the idiv instruction, but what does EDX:EAX mean? LIke if EDX has 7, EAX has 21, ECX has 22 and the instruction is IDIV ECX, how does this operation work?

Hi

EDX:EAX = QWORD value

Greets

Hello, im useing my macro and i looks like this

mDiv MACRO a,b
push NULL
push eax
push edx
push ecx
mov eax,a
mov ecx,b
xor edx,edx
idiv ecx
mov Dword Ptr [esp+12],eax
pop ecx
pop edx
pop eax
endm

i f you want to divide 8 by 2:
mDiv 8,2
pop ;result for example a memory address or a register like eax.

Hi,

IDIV is for Signed Integer Division while DIV is for Unsigned Integer Division

Usage: IDIV src

Modifies flags: (AF,CF,OF,PF,SF,ZF undefined)

Signed binary division of accumulator by source. If source is a byte value, AX is divided by "src" and the quotient is stored in AL and the remainder in AH. If source is a word value, DX:AX is divided by "src", and the quotient is stored in AX and the remainder in DX. If "src" is a dword value, EDX:EAX is divided by "src", and the quotient is stored in EAX and the remainder in EDX.

mov edx, 7 ; most significant dword of qword in edx:eax (positive integer)
mov eax, 21 ; least significant dword of qword in edx:eax (positive integer)
mov ecx, 22 ; "src" (positive integer)
idiv ecx ; Signed Integer Division
; the quotient is stored in EAX (in this case: the positive integer 4DE9 BD38h or 1 307 163 960 decimal)
; the remainder is stored in EDX (in this case: 0000 000Eh or 15t, as per OllyDbg's trace)

In case of a two's complement (thus, negative) qword integer in EDX:EAX (like FFFF FFFFh in edx and FFFF FFEAh in eax, a signed integer of -22 in decimal), the result would be 0000 0000h in edx and FFFF FFFFh in eax, or -1 decimal), like in:

mov edx, -1 ; trace displays EDX = FFFF FFFF
mov eax, -22 ; trace displays EAX = FFFF FFEA
mov ecx, 22
idiv ecx
; once here, EDX = 0 (remainder)
; and EAX = -1 (or FFFF FFFFh, the two's complement representation of -1)

In assembler, the interpretation of such a result is left up to the programmers' intents.

To get the two's complement representation of negative integer -1,
take a 32-bit representation of 1 = 0000 0000 0000 0000 0000 0000 0000 0001
Complement (change to opposite) = 1111 1111 1111 1111 1111 1111 1111 1110
Add 0000 0000 0000 0000 0000 0000 0000 0001 to the "one's complement" you just
obtained by passing 0000 0000 0000 0000 0000 0000 0000 0001
through simple inverters, or NOT gates, if you will, and you
end up with its "two's complement":

1111 1111 1111 1111 1111 1111 1111 1111b, or FFFF FFFFh, or -1t
(The state of the carry flag is always ignored.)

The ALU in the CPU is wired with "adders" (it doesn't know how to subtract, only add).
The reason is, it's much easier to "wire" circuits that add, than circuits that subtract, thus, it's much cheaper to build, and it "saves" a lot of space on the chip (at "micron" scale) for other stuff.

Extend the MSB to all higher positions in order to keep the representation accurate for larger operands (like from DWORD to QWORD, for example). In the example above, EDX = FFFF FFFF "extends" the most significant bit of FFFF FFEA in EAX, by just giving all binary positions of EDX a value of 1 each.

Hope that helps (x'cuze my bad writing)
It's a bit "tricky" but it's useful sometimes.